1. Field of the Invention
This invention relates to the field of data recording and detecting schemes.
2. Background Art
In computer systems, information is stored on magnetic storage systems such as Winchester type hard disks or floppy disks. Data is stored in a series of spiral or concentric rings known as "tracks". The data consists of streams of transitions of polarity of magnetic particles on the disk surface. A number of schemes are used to detect these transitions and data.
One prior art data detection method is a peak detection system. A disadvantage of peak detection schemes is limited data density. Another prior art data detection scheme is known as partial-response class IV (PR-IV) signaling. Systems using PR-IV schemes can achieve higher recording density than the conventional peak detection systems.
In PR-IV systems, input signals are sampled before performing symbol sequence detection. An example of a prior art PR-IV decoder is illustrated in FIG. 1. An input signal is coupled to one terminal of switch 101. The other terminal of switch 101 is coupled to node 102. Node 102 is coupled as an input to symbol sequence detector 103. The output 104 of symbol sequence detector 103 is decoded data. Node 102 is also coupled to a timing recovery circuit indicated by dashed line 105. Timing recovery circuit 105 is comprised of phase detector 106, loop filter 108 and VCO 110. Node 102 is coupled as an input to phase detector 106. The output 107 of phase detector 106 is coupled as an input to loop filter 108. Loop filter 108 provides an output 109 to VCO 110. The output 111 of VCO 110 is a sampling clock signal that controls switch 101.
The timing recovery circuit 105 is required to adjust the clock signal for the sampler so that frequency drifts between oscillators in the send and receive circuits can be compensated for. This timing recovery circuit is typically a phase-locked loop (PLL) consisting of a sampled-data phase detector. The phase detector determines the phase error between the input signal and a VCO by computing the timing gradient from the sampled data values. Timing recovery is described in K. H. Mueller and M. Muller, "Timing Recovery in Digital Synchronous Data Receivers", IEEE Trans. Commun., vol. COM-24, pp. 516-530, May, 1976 and in F. Dolivo etc. in U.S. Pat. No. 4,890,299 entitled "Fast Timing Acquisition for Partial-Response Signaling", and "Fast Timing Recovery for Partial-Response Signaling Systems", F. Dolivo, W. Schott, and G. Ungerbock, IEEE International Conference on Communications, June, 1989, pages 573-577.
Data decoders use phase locked loops to aid in timing recovery. Phase-locked loops (PLL) are essential building blocks for modern communication and storage products. A typical PLL consists of a voltage controlled oscillator (VCO), a phase detector and a loop filter. For many integrated circuits applications, the loop filters are often implemented with external discrete R, C components.
FIG. 2 is a block diagram of a prior art phase locked loop. An input signal Fin 701 is provided as one input into a phase detector 702. The output 703 of phase detector 702 is provided as an input to charge pump 704. Charge pump 704 provides an output 705 to a loop filter, indicated by dashed line 706. Loop filter 706 is external and is coupled to the charge pump at node 707. Node 707 is coupled to ground through resister R1 and capacitor C1. Node 707 provides a VCO Control Voltage Vct as an input to VCO 708. VCO 708 provides an output 709 which is coupled in a feedback loop as a second input to phase detector 702.
Two important parameters are often used to describe the stability and convergence time of a PLL: natural frequency .omega.n and damping factor .zeta.. For the commonly used simple RC loop filter shown in FIG. 7, these values are determined by: ##EQU1## where Kd is the phase detector gain and Kv is the VCO gain.
In many cases, it is very desirable to be able to dynamically change the value of R1. Since R1 is an external component, it is difficult to change its values once it has been chosen.
There are prior art systems that use MOSFETs to switch between different resistor components to change the R1 value. This approach can only have a very limited number R1 values and usually introduces severe disturbance into the loop when switching between components. Also, for integrated circuit applications, this approach requires more pins to accommodate different R1's, and thus increases the cost of the device.